This intention relates to a compound semiconductor device such as GaAs FET (field-effect transistor) and in particular to a method of fabricating a fast compound semiconductor device for use by communication equipment and computers.
In the fabrication of GaAs FETs, a self-alignment process, which employs a refractory metal gate for the formation of an LDD (lightly-doped drain) structure, is widely used with a view to reducing both the parasitic source-drain resistance between gate and source and the parasitic source-drain resistance between gate and drain and with a view to increasing both the gate-source breakdown voltage and the gate-drain breakdown voltage.
An example of such a process is illustrated with reference to FIGS. 15a-g.
FIG. 15a shows a step of the fabrication of a FET. A photolithography process is employed and an n layer 13 acting as a channel layer is formed by implanting n-type impurity ions at a low concentration into a predetermined region of a semi-insulative GaAs substrate 11. This is followed by the deposit of a refractory metallic film 18a on the n layer 13. Further, a photolithography process is carried out to form an etch mask 16 on the refractory metal film 18a. This etch mask 16 is formed of, for example, aluminum (Al) and has a patten length of about 0.5 .mu.m.
Next, as shown in FIG. 15b, an anisotropic etching process is performed using the etch mask 16, to pattern the refractory meatal film 18a to form on the n layer 13 a refractory metal gate electrode 18a which models itself in shape on the etch mask 16. The gate electrode 18 therefore has a gate length of about 0.5 .mu.m, in other words the gate length of the gate electrode 18 and the pattern length of the etch mask 14 are the same.
Next, as shown in FIG. 15c, the gate electrode 18 is side-etched by means of an isotropic etching process, with the etch mask 16 left on top of the gate electrode 18. The gate length of the gate electrode 18, as a result, is reduced down to less than 0.5 .mu.m.
Next, as shown in FIG. 15d, the etch mask 16 is stripped. Thereafter, a resist mask 30 is formed on the substrate 11 in such a way as to have an opening to a region where the n layer 13 is formed. Ions of an n-type impurity are implanted at a low concentration using the resist mask 30 and the gate electrode 18 as masks, to form an n' layer 19a on the source side and an n' layer 19b on the drain side. Hereinafter, the n' layer 19a is called the source-side (SS) n' layer while the n' layer 19b is called the drain-side (DS) n' layer.
An ion implantation process is carried out through an SiO.sub.2 film which is hereinafter called the through (THRU) film 20. As shown in FIG. 15e, the THRU film 20 is deposited on the entire surface of the substrate 11. A resist mask 31 is formed on the THRU film 20 in such a way as to shield (A) a region extending from near the center of the gate electrode 18 to an area of the drain-side n' layer 19b and (B) regions other than the remaining area of the drain-side n' layer 19b and the entire area of the source-side n' layer 19a. Subsequently, ions of an n-type impurity are implanted at a high concentration. As a result of such an ion implantation process, a source-side (SS) n.sup.+ layer 21a is formed in a substrate region on one side of the gate electrode 18 while a drain-side (DS) n.sup.+ layer 21b is formed in another substrate region on the other side of the gate electrode 18. These n.sup.+ layers 21a and 21b have the same width. At the same time, the n' layers 19a and 19b are defined such that the width of the n' layer 19b is greater than the width of the n' layer 19a. Each n.sup.+ layer 21a, 21b has a greater depth than each n' layer 19a, 19b. Each n' layer 19a, 19b has a greater depth than the n layer 13.
Next, as shown in FIG. 15f, the resist mask 31 is stripped. Thereafter, a cap film 22, which is an SiO.sub.2 insulating layer, is deposited over the substrate and the gate electrode 18. Subsequently, an annealing process is carried out to activate implanted impurity ions for the formation of active layers of the FET.
Next, as shown in FIG. 15g, source/drain electrodes 23, 23 are formed on the n.sup.+ layers 21a and 21b, respectively.
The FET thus formed has a short gate length of less than 0.5 .mu.m. This allows the FET to operate at a speed high enough to track high-frequency signals. Additionally, since the gate-drain distance is longer than the gate-source distance, this makes it possible to reduce the resistance of the source region. Further, the gate-drain breakdown voltage can be maintained at high level.
The above-described self-alignment process, however, suffers from the following drawbacks.
The first drawback is due to the fact that refractory metals usually have high resistivity. Therefore, the gate electrode 18, which has a short gate length and is composed of a refractory metallic film, has a high gate resistance, therefore preventing the FET from tracking high-frequency signals. The following approach may be taken in order to reduce the resistance of the gate. An insulating film for planarization is deposited on the entire surface of the substrate 11 of FIG. 15a. A photoresist is applied onto the insulating film. This photoresist is subjected to an etchback process by dry etching to expose the surface of a refractory metallic film forming the gate electrode 18. Subsequently, a low-resistivity metal layer is formed on the gate electrode 18. This approach, however, has some problems. For example, such an etchback process presents the problem that the substrate surface becomes non-uniform because of the deposit of the planarization insulating film and the dry etching process. As a result, it becomes difficult to uniformly expose the gate electrode 18 and the number of fabrication steps increases.
The second problem is due to the fact that the alignment accuracy of the lithography is about .+-.0.1 .mu.m. For the case of FETs with a gate length of below 0.5 .mu.m, there exists a possibility that an n.sup.+ layer is formed, at the time of an impurity ion implantation step for the formation of source/drain regions, in a region near the gate electrode 18 within the DS n' layer 19b if the resist mask 31 undergoes an offset toward the drain in the FIG. 15e step.
The third problem arises when employing W or WSi with a great W composition as a refractory metal to reduce the gate resistance. Etching progresses fast in a direction along the grain boundary of crystals of a crystallized refractory metallic film in the FIG. 15c step in which the gate length is reduced down to less than 0.5 .mu.m. As a result, the post-etch gate electrode is likely to have a disturbed side-surface shape. Therefore, a desirable gate length conforming to the design value may not be achieved.